Yi-Chen Lu

Welcome to my page! I am a Research Scientist at Nvidia Design Automation Research group who is enthusiasitc to optimize modern VLSI chip design flows in a global and systematic manner. Particularly, I devise Machine Learning (ML), algorithmic, and analytical algorithms to guide Physical Design implementations towards optimal PPA. I earned my Ph.D. and M.S. degrees from Georgia Tech Computer-aided Design Lab (GTCAD) advised by Prof. Sung Kyu Lim. During my PhD study, I am extremely grateful to collaborate with Synopsys (2022, 2021, 2020), Nvidia (2022), and Qualcomm (2019) to conduct state-of-the-art research in Electronic Design Automation (EDA). I won the best paper award at 60th Design Automation Conference (DAC, 2023) on the topic of Reinforcement Learning (RL) for conccurent clock and data optimization.

Education

• Ph.D. in Electrical and Computer Engineering, Georgia Institute of Technology, 08/2018 - 05/2023
  Deep gratitude to Prof. Sung Kyu Lim for advising my Ph.D. research.
  Thesis: Machine Learning in Physical Design for 2D and 3D Integrated Circuits


• M.S. in Electrical and Computer Engineering, Georgia Institute of Technology, 08/2018 - 12/2019
  Selected taken courseworks:
  Advanced VLSI, Computer Architecture, Random Processs, Statistical Machine Learning, Convex Optimization, Advanced Graph Algorithms, Physical Design Automation, Machine Learning for Trading, Online Decision Making in Machine Learning, Advanced Programming Techniques, Bitcoin and Cryptocurrency, Probabilistic Graphical Models, Stochastic Process I.


• B.S. in Electrical Engineering, National Taiwan University, 09/2013 - 05/2017
  Deep gratitude to Prof. Yao-Wen Chang for advising me preliminary research in Physical Design.
  GPA: 3.89 / 4.3 (should do better I know...)


• High school diploma from Taipei Municipal Jianguo High School (建國中學), 09/2011 - 05/2013
  12-time top-3 (with 6-time top-1) in midterm/final exams with certificates.

First-Author Publications

• RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning
  Yi-Chen Lu, Wei-Ting Chan, Deyuan Guo, Sudipto Kundu, Vishal Khandelwal, and Sung Kyu Lim.
  60th ACM/IEEE Design Automation Conference (DAC), 2023. Best Paper Award.
  


• DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning
  Yi-Chen Lu, Haoxing Ren, Hao-Hsiang Hsiao, and Sung Kyu Lim.
  27th ACM International Symposium on Physical Design (ISPD), 2023.


• On Advancing Physical Design using Graph Neural Networks (Invited)
  Yi-Chen Lu and Sung Kyu Lim.
  41th IEEE International Conference on Computer-Aided Design (ICCAD), 2022.


• Placement Optimization via PPA-Directed Graph Clustering
  Yi-Chen Lu, Tian Yang, Sung Kyu Lim, and Haoxing Ren.
  4th ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2022. Nominated to Best Paper Award.


• Driving Early Physical Synthesis Exploration through End-of-Flow Total Power Prediction
  Yi-Chen Lu, Wei-Ting (Jonas) Chan, Vishal Khandelwal, and Sung Kyu Lim.
  4th ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2022.


• Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning
  Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, and Sung Kyu Lim.
  40th IEEE International Conference on Computer-Aided Design (ICCAD), 2021.


• RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning
  Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, and Sung Kyu Lim.
  58th ACM/IEEE Design Automation Conference (DAC), 2021.


• The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks
  Yi-Chen Lu, Sai Surya Kiran Pentapati, and Sung Kyu Lim.
  25th ACM International Symposium on Physical Design (ISPD), 2021. Nominated to Best Paper Award.


• VLSI Placement Optimization using Graph Neural Networks
  Yi-Chen Lu, Sai Surya Kiran Pentapati, and Sung Kyu Lim.
  34th Advances in Neural Information Processing Systems (NeurIPS) Workshop on ML for Systems, 2020.


• A Fast Learning-Driven Signoff Power Optimization Framework
  Yi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, and Sung Kyu Lim.
  39th IEEE International Conference on Computer-Aided Design (ICCAD), 2020.


• TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs
  Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, and Sung Kyu Lim.
  57th ACM/IEEE Design Automation Conference (DAC), 2020.Nominated to Best Paper Award.
  Acceptance Rate: <1%


• GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization
  Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, and Sung Kyu Lim.
  38th IEEE International Conference on Computer-Aided Design (ICCAD), 2019. Nominated for Best Paper Award.
  Acceptance Rate: <1%

Work Experience

• Nvidia, Research Scientist, 06/2024 - now
  
  • Developing novel ML algorithms for EDA.
    
• Apple, Physical Design Methodology and Machine Learning, 04/2023 - 06/2024
  
  • Developed ML and GPU-acceleration techniques for PPA optimization.
    
• Synopsys, Research Intern, 05/2022 - 12/2022
  
  • Developed machine learning algorithms to achieve better timing-power tradeoff.
    
  • Contributed production code to Integrated Circuit Compiler II (ICC2) in C++ and Python.
• Nvidia, Research Intern, 01/2022 - 05/2022
  
  • This work is selected for a US Patent.
  • Developed a placement optimization method using graph learning for in-house designs.
    
  • Developed a an early timing prediction framework that improves chip design turn-around time.
• Synopsys, Research Intern, 05/2021 - 08/2021
  
  • Developed a machine learning based framework for timing bottleneck cell prediction.
    
  • Contributed production code to Integrated Circuit Compiler II (ICC2) in C++ and Python.
• Synopsys, Research Intern, 05/2020 - 12/2020
  
  • This work is selected for a US Patent.
  • Developed a discrete gate sizing methodology for timing optimization using deep reinforcement learning.
    
  • Contributed production code to Integrated Circuit Compiler II (ICC2) in C++ and Python.
    
• Qualcomm, Research Intern, 05/2019 - 08/2019
  
  • Enhanced physical design methodologies by devising deep learning and graph learning algorithms.
    
  • Involving projects include yield prediction, power-performance-area (PPA) optimization, and congestion mitigation.
• Gatos Vision, Research Intern, 05/2018 - 08/2018
  
  • Devised machine learning algorithms for video summarization and object detection.
• IBM, Machine Learning / Cloud Software Engineer, 07/2017 - 12/2017
  
  • Developed Chinese chatbot using natural language processing algorithms, and hosted on cloud servers.
    
  • Developed IoT systems such as racket speed sensor and intelligent reception robot.
• MediaTek, Software Enginner Intern, 07/2016 - 04/2017
  
  • Developed algorithms to enhance Electronic Design Automation softwares using C++ and TCL.

Competition Achievements

• Citadel Terminal Summer Global Coding Competition, July 2021, global
  
  • Developed a strategic game-based AI using python in a team of three members.
    
  • 10th place out of 100+ selected competitors worldwide. Prize: 1k USD.
• Shanghai Commercial and Saving Bank Fintech Hackathon, Nov 2017, Taipei
  
  • Developed a blockchain-based credit transfer application on Android in a team of three members.
    
  • Honorable mention out of 89 competitors. Prize: 30k NTD.
• National Taiwan University Hackathon, Jul 2017, Taipei
  
  • Developed a machine learning framework to predict county-wise monthly power demand in a team of two members.
    
  • First Prize Award out of hundreds of competitors. Prize: 30k NTD.